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    module three_state (i1, ena, out);
  input i1, ena ;
  output out;
  assign out = ena ? i1 : 1'bz;
endmodule
 
    module mux (i0, i1, sel, out);
  input i0, i1, sel ;
  output out;
  assign out = sel ? i1 : i0;
endmodule
 
    module dff (d, clk, q);
  input d, clk;
  output q;
  reg q;
  always @(posedge clk)
    q = d;
endmodule
 
 
module L_LEVEL(PULSE, M0, M3, C1, D1, RES);
  input D1, C1, M0, M3, RES;
  output PULSE;
  reg P31, P01;
  wire L_P31, L_P01;
  assign PULSE = P31 & ~P01;
  assign L_P31 = M3 & C1;
  assign L_P01 = M0 & C1;
  always @(RES or L_P31 or D1) begin
    if (!RES) P31 = 0;
    else if (L_P31) P31 = D1 ;
  end
  always @(RES or L_P01 or P31) begin
    if (!RES) P01 = 0;
    else if (L_P01) P01 = P31;
  end
endmodule
 
    module H_LEVEL(PULSE, M3, C1, D1, RES);
   input D1, C1, M3, RES;
  
output PULSE;
  
reg [1:0]state;
  
wire [1:0]tmp;
  
assign tmp = state;
  
assign PULSE = tmp[1];
  
parameter [1:0]
    
Wait_H = 2'b00,
    
OutPULSE = 2'b10,
    
Wait_L = 2'b01;
  
always @(negedge RES or negedge C1) begin
    
if (!RES) state = Wait_H;
     else begin
    
 case (state)
       Wait_H: if (D1 & M3)
         state <= OutPULSE;
       OutPULSE: state <= Wait_L;
       Wait_L: if (!D1) state <= Wait_H;
      endcase
     end
  end
endmodule
 
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