Integrated Support from Prototype Production and Development to Volume Production

MEMS Foundry Service

DNP will provide a dedicated Micro Electro Mechanical Systems (MEMS) foundry service, customizing products to client needs from a neutral standpoint. Contracts will also be accepted for outsourced single process and partial process work.

Contents 

 

MEMS Foundry Service Features

MEMS Technology: A Potential Example

Interposer Features

Foundry Performance

External Releases

 

 

MEMS Foundry Service Features

 

●DNP operates a pure-play MEMS foundry service, customizing products to client needs, and will not act as a market competitor by marketing DNP-branded products

●DNP provides integrated support from prototype production through development to volume production.

●Contracts will also be accepted for outsourced single process and partial process work.

●DNP’s technology is capable of fabricating φ 6 or 8 inch silicon or glass wafers.

 

MEMS Solutions from DNP

 Dedicated MEMS Foundry

The DNP MEMS foundry is a pure-play initiative that customizes products to client needs, and will not act as a market competitor. As photomasks are manufactured in-house it is possible to ensure the confidential nature of critical information, such as patterns. DNP will provide integrated support from prototype production through development to volume production.

 

 Development and Volume Production Line

DNP maintains a dedicated MEMS development and manufacturing line that is capable of fabricating φ 6 or 8 inch wafers.

 

 

 

 

 Extensive Track Record and Broad-Based Services

DNP offers a service based on the fabrication and production know-how developed in the prototype production and mass-produced products provided for more than 300 proto-types in the period since 2001

 

 

 

 Through Silicon Via (TSV) Wiring Board

DNP offers a service based on TSV and interposer technology that capitalizes on DNP-developed copper plating technology.

 

 

 

 Broad-based Services

DNP offers a variety of services based on an in-house technology platform that includes a MEMS package service, ultra high precision mold outsourcing services, and microfluidic chip outsourced fabrication services.

  

 

 

Service Flow

The following diagram represents the service flow undertaken by a dedicated DNP project manager. 

 

Dedicated MEMS Development and Volume Production Line

     

     

    Capable of fabricating φ6/8 inch wafers
    Air cleanlines sclass 10, 1,000, 10,000 separate air conditioning management
    Wafer particle and contamination controlled
    ISO9001: 2008 certification
    Location: Kashiwa City, Chiba Prefecture

Facilities

Process category

Facility

Photolithography

 Coater and developing equipment

 Proximity aligner

 Double sided aligner

 i-line stepper

Lamination

 Vacuum laminator (PI film, dry film and adhesive sheet)

Thin Film Deposition

 PE-CVD(SiO2 / SiN / a-Si)

 LP-CVD(poly-Si)

 Sputtering equipment (AI, AU, Cr, Cu, Ti, TiN・・・)

 EB deposition apparatus(Cr, Cu, Ti)

Diffusion Furnace

 Thermal oxidation (Wet / Dry)

 Thermal diffusion furnace/ Sinter furnace

 Organic annealing furnace

Dry Etching

 Deep RIE device

 Silicon RIE device

 Asher

Wet Etching

 Silicon anisotropic etching device

 Silicon oxide film etching device

 Metal etching device

Cleaning

 APM / SPM / acid cleaning

 Organic solvent removal

 Polymer peeling

Electroplating

 Cu-filled plating

 Ni / Au / Cu plating

Bonding and Dicing

 Anodic bonding device

 Dicing device

 Pick-upper device

 Two fluid cleaning device

Measurement

 CD-SEM / Observation SEM

 Optical / Laser / Double view microscope

 IR microscope

 3D laser measuring device

 Stylus profilometer

 Ellipsometer

 Substrate warping measuring device

 Spread resistance profiling equipment

 Prober

 Total internal reflection fluorescence X-ray analysis device

 Contamination inspection equipment

 Visual inspection device

 Environmental testing equipment (Constant temperature and humidity

 chamber, hot-cold shock, HAST)

Outsourcing

 Grinding and polishing etc.

 

 

  Back to Top

 

 

 

 

MEMS Technology: A Potential Example

 

Major Technology and Process Spec

Major technology

Process

Process spec

Notes

Size

Deep Silicon Etching

Deep RIE

Minimum line width: L/S 1.5μm

Aspect Ratio: 100

Cone angle: 90 +/- 1

(All dependent on patterning)

Through-substrate processing possible SOI front and rear surfacing also possible

φ6/8

inch

Anisotropic Etching

TMAH wet etching

Within 5% of the plane surface against depth

Through-substrate processing possible SOI front and rear surfacing also possible

Thin Film Deposition

PVD

Film thickness uniformity: Within 5% of the plane surface (With the exception of TiN)

Through-substrate deposition possible Substrate front and rear surfacing also possible Al, AlNd, AlCu, Cr, Cu, Au, Ti, TiN

CVD

Film thickness uniformity : Within 5% of the plane surface

Through-substrate processing possible SOI front and rear surfacing also possible SiO, SiN, a-Si

Bonding

Anodic bonding(Silicon/glass)

Sealing internal pressure>0.01Pa

Si/glass/Si possible Glass/Si/glass also possible Fusion bond

Laminating

Vacuum laminating

Conformal Resist Coverage Bubble-free

Nega Resist Process

Plating

Cu-filled plating

Aspect Ratio: 50 Void-free

Wiring plating responses possible (Cu, Au)

 

Technology Example

    Photolithography Technology

Fine pattern lithography: (i-line stepper)

Resist thickness: 1μm

 L/S = 0.5 / 0.5μm

 

 

 

 

 

 

 

 Film thickness lithography (Both side aligner)

 Resist thickness: 20μm

 L/S = 10 / 10μm

 

 

 

 

 

 

 

    Laminating Technology

     Lithography on the surface of a through-hole substrate using resin film 

     

     

     

     

     

     

     

     

     

 

    Deposition Technology

      

     

    SiO2 deposition (PE-CVD)

    Film thickness: ~20μm

    Temperature: 200 ~ 400℃

     

     

     

     

     

     

     

     

     

     

    Deep RIE Technology

     

    High aspect fabrication

    Aspect ratio: ~70

     

     

    Cu-Filled Plating Technology

     

    Through VIA cross section                Radiographic photo

     

     

    Cu thick-film wiring plating technology

     

 

Specialized Fabrication Example

    Fabrication Technology

     

    Configuration of cone shapes through Deep RIE

     

     

    Specialized Wiring Technology

            

     

    Configuration of sidewall electrode for through hole

    Configuration of wiring to surface of through hole (polyimide, plating)

     

     

     

    Configuration of wiring for stepped structure

     

     

     

    TSV and Rewiring for Finely Patterned Multilayer Substrate (Under Development)

     

     

     

    TSV and rewiring fabrication for finely patterned multilayer substrate (M1~M4: Cu damascene wiring)

    Both side rewiring possible

 Back to Top

 

 

 

 

Interposer Features

 

High Density System, Miniaturization, and High Functionality Responses

DNP provides a TSV and rewiring fabrication service applying deep silicon etching, fine plating and thin film deposition technology etc

 Features

 ● High density through hole electrode

 ● Cu plating voidless filling based on uniquely developed DNP technology

 ● Build up fine wiring layer based on semi-additive processes

 ● Superior high frequency characteristics based on the use of high resistance Si wafers and glass

       wafers

 ● Via-last fabrication (Si) of device wafers [Unfilled types can also be customized]

 ● Superior electrical characteristics based on die-electric interlayer insulation materials

 ● We also offer Cu filling with no voids in the high aspect ratio through hole

 Si

 ● Silicon interposer

 ● Via-last fabrication of device wafers (Package

       fabrication)

 ● Wiring board

 

 TSV (Through Silicon Via) Cross Section

 

 Glass (under development)

 ● Glass interposer

 ● Wiring board

 

 

Type

Application examples

Structure and features

Si

Glass

TSV (Via First) Various interposers

Configuration of TSV and wiring layer

Yes

Yes

PKG board
(Via Last)
Various devices

Configuration of TSV and wiring layer on device Fabrication of wafer level PKG

Yes

No

Wiring board Probe card

Configuration of multi-layer wiring layer on surface of board

Yes

Yes

 

Interposer Categories

Type

Cross section image

Features

Application examples

TSV

 

Configuration of through hole with MEMS fabrication at later stage, based on DNP standard specifications, and the provision of partial functions to the interposer with (Composite substrate)

Example)

● Passing through liquid/light (radio waves)

● Hole for visibility purposes

● Hole for mechanical fabrication purposes

● Interposers for Industrial devices

● Interposers for high frequency devices

● Others

PKG board

 

We aim to miniaturize packaging using via-last techniques to configure TSV for circuit boards (pre-configured for devices) provided by client (packaging configuration)

● Various sensor boards for industrial uses

● Others

Wiring board

 

 

(Under development)

 

Multi-layering of wiring layer using fine wiring technology

More advanced multi-layering that improves warp and flatness is also in development. (Wiring board)

● Wiring board for probe card

● Others

 

DNP Standard Specification (Interposer)

DNP offers customized structures based on standard specifications

Standard specifications

Core substrate

Si

Glass

Number of layers

2 layers front and rear

Insulating layer material

Polyimide

Insulating layer thickness

4~8μm

Wiring materials

Cu, Cu / Ni / Au

Wiring line / space

Cu only: 10μm / 10μm

Cu / Ni / Au: 15μm / 15μm

Wiring layer thickness

1~6μm

Via diameter / land diameter

φ30μm / φ40μm~

Core materials

Silicon (high resistance, low resistance)

Glass

Core size

φ6 inch / φ8 inch

Core thickness

400μm (φ6 inch / φ8 inch)

Through hole materials

Cu

Through hole diameter

φ50μm

φ50~80μm

Through hole pitch

>200μm

Land diameter

>100μm

Build up layer

Si

Glass

Number of layers

2 layers front and rear

Insulating layer material

Polyimide

Insulating layer thickness

4~8μm

Wiring materials

Cu, Cu / Ni / Au

Wiring line/space

Cu only: 10μm / 10μm

Cu / Ni / Au: 15μm / 15μm

Wiring layer thickness

1~6μm

Via diameter / land diameter

φ30μm / φ40μm

※Customized orders will be handled on an individual basis

     

Silicon Interposer Cross Section Structure

Option example: Si through hold fabrication

(Si through hole configured following TSV, rewiring configuration)

 

Back to Top

 

 

 

 

Foundry Performance

 

DNP has capitalized on its neutral position as a company offering a pure-play foundry that does not produce in-house products, to create a track record in a variety of industries and provide more than 300 prototypes and volume production systems to in excess of 150 companies both in Japan and overseas.

 

Application

Category

Targets

Functions

Structural Features

Industrial fields

Micro-nozzle

Flow channel

Liquid

(Inks, drug solutions etc.)

Through-use

Hole

Industrial, medical and electronic equipment

Microchip

Groove

Medical and bio-equipment

Light shielding plate

Slit

Light

(Ultraviolet light, e-beams etc.)

Micro-filter

Hole

Optical elements

Groove

Optical and communications equipment

E-beam Aperture

Hole

Semi-conductor equipment

Precision shielding plate

Optical components

Jig

Communications component

Fixed use

Communications equipment

Mold

Die

Shape

Replication

Pillar

Optical and bio-equipment

 

 

The production of fine specialized structure bodies based on MEMS fabrication (switching out of metallic and resin components).

DNP aims to help clients achieve their goals using our fabrication and production know-how developed through our rich fabrication track record.

 

Back to Top

 

 

 

 

External Releases

 

■Development of Silicon Interposer, The Institute of Electrical Engineers of Japan 2010

 

■Development of High Density Wiring Technology and Interconnect Technology with Silicon Through-hole ECWC 2010 (Electronic Circuits World Convention)

 

■Status and prospects for TSV-based Si interposers and 3-dimensioanl integration technology, Electronic Journal, Technical Information Institute 2012

 

■Development of Si Interposer for 2.5D-3D Advanced Package, International Conference on Electronics Packaging 2012

 

■Cost Effective Interposer for Advanced Electronic Packages, Electronic Components and Technology Conference 2014

 

Back to Top